Testbench components

eVC ARCHITECTURE: eVC is an e Verification Component. It is ready –to-use, configurable verification environment.

       Agents are the key to eVC architecture. Agents are either active or passive. Active  agents are agents that drive DUT signals. Passive agents never drive signals, either because they just monitor an interface within the DUT or because, according to the protocol, no signals ned to be driven.

Types of Agents:

i.        MASTER AGENT: A transmit agent that can send data to the DUT’s receive port. It can be either active or passive.

ii.      SLAVE AGENT: A receive agent that can collect data from the DUT’s transmit port. It can be either active or passive.

Description of all the components :

1. Config.

It decides whether the agent is active or passive

2. Sequence

Sequence is a class which is used to generate some random input, it has the set of random inputs that is stored in seq_lib. Test case is nothing but the set of inputs to test the DUT which forms Sequence library.

3. Sequencer:

A sequencer is an advanced stimulus generator that controls the items that are provided to the driver for execution. By default, a sequencer behaves similarly to a simple stimulus generator and returns a random data item upon request from the driver. This default behavior allows you to add constraints to the data item class in order to control the distribution of randomized values

.

5. Driver:

The driver’s role is to drive data items to the bus following the interface protocol. The driver obtains data items from the sequencer for execution. The UVM Class Library provides the uvm_driver base class, from which all driver classes should be extended, either directly or indirectly.

6. Monitor

Monitor is used to sample input and output at DUT ] interfaces.

7. Scoreboard

It generates true output for the random input that is generated by the sequences. As input is detected, data will be added to the scoreboard as a list. When output is detected, it will be compared against scoreboard data in the list.

8. Checker

Checker is used to match the output data with the expected output (to verify the output).

9. Functional Coverage

It checks the functional coverage and tells if the test plan goals have been met.

There are 3 types of functional coverage

Basic item coverage, transition item coverage, cross coverage

a)      Basic Item Coverage: This coverage tells if all legal values of an interesting variable have been covered.

b)      Transition Item Coverage: This coverage is used for state machines which form the control logic for any design. It tells if all legal transitions of a state machine have been covered.

c)       Cross Coverage: This coverage allows to examine the cross product of two or more basic or transition items to check if all interesting combinations of basic and transition items have been covered

Driver in system verilog

The driver’s role is to drive data items to the bus following the interface protocol. The driver obtains data items from the sequencer for execution. The UVM Class Library provides the uvm_driver base class, from which all driver classes should be extended, either directly or indirectly.

Callback in system verilog or verification

Callback is mechanism of changing to behavior of a verification component such as driver or generator or monitor without actually changing to code of the component. 

Interview Questions Collection

1. What is callback ?

2. What is factory pattern ?

3. Explain the difference between data types logic and reg and wire

4. What is the need of clocking blocks ?

5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?

6. Explain Event regions in SV.

7. What are the types of coverages available in SV ?

8. What is OOPS?

9. What is inheritance and polymorphism?

10. What is the need of virtual interfaces ?

11. Explain about the virtual task and methods .

12. What is the use of the abstract class?

13. What is the difference between mailbox and queue?

14. What data structure you used to build scoreboard

15. What are the advantages of linkedlist over the queue ?

16. How parallel case and full cases problems are avoided in SV

17. What is the difference between pure function and cordinary function ?

18. What is the difference between $random and $urandom?

19. What is scope randomization

20. List the predefined randomization methods.

21. What is the dfference between always_combo and always@(*)?

22. What is the use of packagess?

23. What is the use of $cast?

24. How to call the task which is defined in parent object into derived class ?

25. What is the difference between rand and randc?

26. What is $root?

27. What is $unit?

28. What are bi-directional constraints?

29. What is solve...before constraint ?

30. Without using randomize method or rand,generate an array of unique values?

31. Explain about pass by ref and pass by value?

32. What is the difference between bit[7:0] sig_1; and byte sig_2;

33. What is the difference between program block and module ?

34. What is final block ?

35. How to implement always block logic in program block ?

36. What is the difference between fork/joins, fork/join_none fork/join_any ?

37. What is the use of modports ?

38. Write a clock generator without using always block.

39. What is forward referencing and how to avoid this problem?

40. What is circular dependency and how to avoid this problem ?

41. What is cross coverage ?

42. Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them

43. How to kill a process in fork/join?

44. Difference between Associative array and Dynamic array ?

45. Difference b/w Procedural and Concarent Assertions?

46. What are the advantages of SystemVerilog DPI?

47. How to randomize dynamic arrays of objects?

48. What is randsequence and what is its use?

49. What is bin?

50. Why always block is not allowed in program block?

51. Which is best to use to model transaction? Struct or class ?

52. How SV is more random stable then Verilog?

53. Difference between assert and expect statements?

54. How to add a new processs with out disturbing the random number generator state ?

55. What is the need of alias in SV?

56. What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?

57. How different is the implementation of a struct and union in SV.

58. What is "this"?

59. What is tagged union ?

60. What is "scope resolution operator"?

61. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?

62. What is the difference between




view source

print?

1.logic data_1;

2.var logic data_2;

3.wire logic data_3j;

4.bit data_4;

5.var bit data_5;




63. What is the difference between bits and logic?

64. Write a Statemechine in SV styles.

65. What is the difference between $rose and posedge?

66. What is advantage of program block over clockcblock w.r.t race condition?

67. How to avoid the race condition between programblock ?

68. What is the difference between assumes and assert?

69. What is coverage driven verification?

70. What is layered architecture ?

71. What are the simulation phases in your verification environment?

72. How to pick a element which is in queue from random index?

73. What data structure is used to store data in your environment and why ?

74. What is casting? Explain about the various types of casting available in SV.

75. How to import all the items declared inside a package ?

76. Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?

77. What is streaming operator and what is its use?

78. What are void functions ?

79. How to make sure that a function argument passed has ref is not changed by the function?

80. What is the use of "extern"?

81. What is the difference between initial block and final block?

82. How to check weather a handles is holding object or not ?

83. How to disable multiple threads which are spawned by fork...join


84 Why cannot initial statement be synthesizeable ?


85 Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?





86a What is the difference between blocking and nonblocking assignments ?


86 What is the difference between wire and reg data type ?


87 Write code for async reset D-Flip-Flop.


88 Write code for 2:1 MUX using different coding methods.


89 Write code for a parallel encoder and a priority encoder.


90 What is the difference between === and == ?


91 What is defparam used for ?


92 What is the difference between unary and logical operators ?


93 What is the difference between tasks and functions ?


94 What is the difference between transport and inertial delays ?


95 What is the difference between casex and case statements ?


96 What is the difference between $monitor and $display ?


97 What is the difference between compiled, interpreted, event based and cycle based simulators ?


98 What is code coverage and what are the different types of code coverage that one does ?


99 How will you handle multiple interfaces in UVM.


100 Explain APB and AHB using state machine


101 Explain Polymorphism and Inheritance using examples.


102When to use blocking and when to use non-blocking assignments.


103How do you control sequences in UVM {through testcase}.






1. Explain NAND flash operation


2. Diff btwn task & function


3. Types of arrays.


4. Advantage of dynamic array over associative array


5. Can you declare everything as associative array?


6. Explain packed and un packed array


7. Types of sequences


8. Explain ahb signals


9. Explain in details split and retry in hresp


10. Diff btwn @posedge and $rose


11. Uvm how driver and sequencer interact


12. How data passes from layer to layer in uvm


13. Diff btwn reg n wire


14. Diff between blocking n non blocking


15. Draw waveform for the code


Module ex;


Input [2:0] a;


Begin


a<= 3’b000;


a<=#5 3’b010;


a = #10 3’b101;


a<= #20 3’b111;


end


endmodule


16. How do you pass an array to a function.


17. About PREADY signal: is there a PREADY input to the slave


18. Without constraint, how will u generate random number between the range ‘x’ and ‘y’.


19. How to reduce the number of clock cycles taken for a transfer in APB/AHB protocol.. Eg: suppose a transfer takes 4 clock cycles, how can we make it in 3.


20. What does an ISR do. Suppose you have to write an isr, what all things you will write in that handler.


21. SIMULATOR related: when we compile any code, we give a filelist and the compiler compiles all the files in the list. Suppose some of the files is calling another file(`include option), then how will we compile that included file/directory


22. Basic verification approach: how will you verify an IP, in an SOC environment… how will you build the VC(approach).


23. Why sv over Verilog( explain properties of oops)


24. What is inheritance and polymorphism explain with example


25. Why/explain casting is used in terms of class and handles


26. Data types in sv


27. Randomization?


28. Cyclc randomization


29. How probability distribution is achived


Ex. 50% of time a =0


25% of time a = ( 1 - 1000)


25% of time a = (1001 – 2^32 - 1) how do you achieve this


30. Explain wait, randcase


31. Explain semaphore and mailboxes?


32. Mailboxes how does it work


33. Diff btwn mailbox and Que


34. Explain addr phase and data phase in AHB


35. Explain uvm flow


36. As soon as you get the spec how do you start verification


37. Why phases are required

Interview Question related to Mux, gates

1. EX-NOR gate using 2:1 mux 

In a 2:1 Mux ,

Give 2nd input as A and 1st input as A bar .
and give B as a Select line...

final output y = Output of EXNOR 


//add your inputs/questions/articles/solutions in the comment section.
Thank you !

If else and case statements

1. Nested if else create priority encoder so better to use case statements
2. Full case: all possible branches are defined
3. Parallel case: all case items are mutually exclusive

Randomization methods in SV : Part 1

Randomization Methods

(i)randomize()
  a) Variables in an object are randomized using the randomize() class method.
  b) Every class has a built-in randomize() virtual method, declared as:

virtual function int randomize();

c) The randomize() method is a virtual function that generates random values for all the active random variables in the object, subject to the active constraints.

d) The randomize() method returns 1 if it successfully sets all the random variables and objects to valid values, otherwise it returns 0.

Example: class SimpleSum;
rand bit [7:0] x, y, z;
constraint c {z == x + y;}
endclass

(ii)pre_randomize() and post_randomize():
Every class contains built-in pre_randomize() and post_randomize() functions, that are automatically called by randomize() before and after computing new random values.

The built-in definition for pre_randomize() is:

function void pre_randomize;
if (super) super.pre_randomize(); // test super to see if the
// object handle exists
// Optional programming before randomization goes hereendfunction

The built-in definition for post_randomize() is:

function void post_randomize;
if (super) super.post_randomize(); // test super to see if the
// object handle exists
// Optional programming after randomization goes hereendfunction

//example for pre post randomization 

program pre_post_rand;
class eth_pkt ; 
rand integer length ; endclass 
class my_pkt extends eth_pkt ;
function void pre_randomize() ;
super.pre_randomize() ;
$display("before randomize length = %h" , length ) ;endfunction 
function void post_randomize() ;
super.post_randomize() ;
$display("After randomization length =%h", length ) ;endfunctionendclass 
my_pkt m_pkt ; 
initial begin 
m_pkt = new() ;
m_pkt.randomize() ;endendprogram 

(iii)Disabling random variables with rand_mode():

The rand_mode() method can be used to control whether a random variable is active or inactive. When a random variable is inactive, it is treated the same as if it had not been declared rand or randc. Inactive variables are not randomized by the randomize() method, and their values are treated as state variables by the solver.

All random variables are initially active.

The syntax for the rand_mode() method is:

task object[.random_variable]::rand_mode( bit on_off );

// example to explain rand mode operation 

program rand_mod ;
class eth_pkt ; 
rand integer length ; 
rand bit [47:0] dst_addr ; 
constraint valid_len 
{
length >=5 ; length <= 10 ; 
} 
task print () ; 
$display("the length is %h" , length) ; endtask endclass 
eth_pkt pkt ; 
initial begin 
pkt = new () ; 
pkt.length.rand_mode(1) ; // rand mode is on u can make it 1 or 0 
if( pkt.randomize() == 1 ) 
begin 
$display("randomization success") ; 
pkt.print (); end 
else 
$display("randomization fail") ; end endprogram 

(iv)Controlling constraints with constraint_mode():

The constraint_mode() method can be used to control whether a constraint is active or inactive. When a constraint is inactive, it is not considered by the randomize() method. All constraints are initially active.

The syntax for the constraint_mode() method is:

task object[.constraint_identifier]::constraint_mode( bit on_off );

// example to explain constraint mode operation 

program cnst_mod ;
class Eth_pkt ;
rand integer length ;
constraint valid_len 
{
length >=5 ; length <= 10 ; 
} 
task print () ;
$display("the length is %h" , length) ;endtask endclass 
Eth_pkt pkt ;
initial begin 
pkt = new () ;
pkt.valid_len.constraint_mode (0) ; // constraint mode is off u can make it 1 or 0 
if( pkt.randomize() == 1 ) 
begin
$display("randomization success") ;
pkt.print () ;end 
else 
$display("randomization fail") ;endendprogram