Programming block and Module

always begin 
       @(posedge clk) $display("at the posedge of clk");
       end

and

initial begin 
          forever @(posedge clk) $display("at the posedge of clk");
       end

It is mainly a difference in intent. Some synthesis tools ignore all the code in an initial block thinking they are for simulation only and do not describe hardware to be synthesized.

Technically, there are a few thing you can do with a forever statement that you cannot do with an always block. As a looping statement, you can break out of aforever loop, and if you name the statement, you can disable it. So you can terminate the process created by an initial block. There is no way to terminate the process created by an always block.

Program Block :

The program block came from the Vera verification language that was donated to SystemVerilog. In Vera, a program was a single procedure that represented the "test". Your test was started at time 0 and when the test terminated, the program terminated the simulation. If you needed multiple test threads, you either had to use the fork statement to start it, or use multiple programs. When the last program terminated, the simulation terminated.

As part of the integration with SystemVerilog, the program was turned into a module-like construct with ports and initial blocks are now used to start the test procedure. Because an always block never terminates, it was kept out of the program block so the concept of test termination would still be there.

Today, most people do not utilize this termination feature because the OVM/UVM have their own test termination mechanisms. The program block is no longer a necessary feature of the language other than to help people converting over from Vera to SystemVerilog.

A module can have always block .

Example :

program test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endprogram

Output : 
0 e
0 a
0 d

module test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endmodule

Output : 
0 e
0 a
0 d
10 b
20 c