uvm_phases and flow - Interview Presparation

From the starting of simulation till the end of the simulation:

Why Phases Concept : 
1. In order to have a consistent Testbench flow, UVM introduces “Phases” to synchronize major functional steps a simulation runs through.

2. These steps are sequential in nature which are executed in the following order:

Build Phases:
Where the Testbench is constructed, connected and configured.
Run-time Phases:
Stimulus generation & time-consuming simulation takes place here.
Clean up Phases:
Here the Test results are collected and reported.

We’ll see more details of these 3 Phases in the upcoming section of this post.

1. We know that UVM environment is built of static components those are derived from the UVM base class i.e. uvm_component which contains a number of virtual methods. 

2. These virtual methods support the UVM Phasing mechanism,

3. So UVM phasing mechanism is only for uvm_components

4. Hence a verification component can be developed in isolation since there is an established understanding of what is expected to happen in each of the execution phases.

Diagram 1: UVM Phases

Here we can see 3 groups of Phases which are briefly described as well.
Build Phases group contains 3 sub-phases
Run Phases group contains 13 sub-phases
Cleanup Phases group comprises of 4 sub-phases

How UVM Phasing is triggered?:
1. To start a UVM Testbench, the run_test() method has to be called from the static part of the Testbench. 

2. It is usually called from within an initial block in the top level module of the Testbench.

// Top level Testbench 

module module top_tb; 

// UVM start up: 

initial begin 

uvm_config_db #(virtual bus_if)::set(null, "*", "BUS_vif" , BUS); 

run_test("bidirect_bus_test"); 

end 

endmodule: top_tb 

3. Once the run_test() method is called, it constructs the root component of the UVM environment 

4. then triggers/initiates the UVM Phasing process. 

5. The run_test() method can be passed with a string argument

6.  In the above code argument is “bidirect_bus_test”, to define the default type name which is used as the root node of the Testbench Hierarchy.
7. In addition, run_test() method also checks for a command line plusarg called UVM_TESTNAME and uses that plusarg string to lookup a factory registered uvm_component to override any default type name.
8. Hence to execute the “bidirect_bus_test” using command line plusarg, we’ve to use the following command line:
% <simulator executable> +UVM_TESTNAME=bidirect_bus_test

9. about uvm_test_top and uvm_root (to be updated)

What each of UVM Phase Performs?:
Lets detail out each of the UVM Phase/Sub-Phase with respect to the activities being performed during their execution:
1) Build Phase:
The build phases are executed at the start of the UVM Testbench simulation and their overall purpose is to construct, configure and connect the Testbench component hierarchy. 

All the build phase methods are functions and therefore execute in zero simulation time.

build:
i) Once the UVM Testbench root node component is constructed, the build phase starts to execute. 

ii) It constructs the testbench component hierarchy in a top-down manner. 

iii) During the build phase, uvm_components are indirectly constructed using the UVM factory.

connect:i) The connect phase is used to make TLM connections between components or to assign handles to testbench resources. 

ii) It has to occur after the build method so that Testbench component hierarchy could be in place and it works from the bottom-up of the hierarchy upwards.

end_of_elaboration:
i) The end_of_elaboration phase is used to make any final adjustments to the structure, configuration or connectivity of the Testbench before simulation starts. 

ii) Its implementation can assume that the Testbench component hierarchy and inter-connectivity is in place. This phase executes bottom up.

start_of_simulation:The start_of_simulation phase is a function which occurs before the time consuming part (run-phase) of the testbench begins. It is intended to be used for displaying banners; Testbench topology; or configuration information. It is called in bottom up order.

2) Run Phase:
i) The UVM Testbench stimulus is generated and executed during the run time phases. 

ii) Run phase was present in OVM as well but additional other phases were added to UVM to give finer run-time granularity for tests, scoreboard and other components.
iii) The run phase occurs after the start_of_simulation phase and is used for the stimulus generation and checking activities of the Testbench. 

iv) The run phase is implemented as a task, and all uvm_component run tasks are executed in parallel. 

v) Transactors such as driver and monitor will nearly always use this phase.

pre_reset:
pre_reset phase starts at the same time as the run phase. Its purpose is to take care of any activity that should occur before the reset. E.g. waiting for a power signal to go active.
reset:

As the name indicates, reset phase is especially for DUT or Interface specific reset behaviour. This phase would be used to generate reset to put the DUT/Interface into a default state.

post_reset:
This phase is intended for any activity required just after the reset phase.

pre_configure:
This phase is intended for anything that is required to prepare for the DUT configuration process after the DUT is out of reset.
configure:

configure phase is used to put the DUT into a known state before the stimulus could be applied to the DUT. For example – programming the control registers of the device for a particular test scenario.
post_configure:
This phase is intended to wait for the effect of the configuration to propagate through the DUT.

pre_main:pre_main is used to ensure that all the components needed to generate the stimulus are ready to do so.
main:

the main phase is where the stimulus specified by the Test case is generated and applied to the DUT. It completes in two conditions: One is the stimulus gets exhausted and another is when a timeout occurs. Sequences are started in this phase to generate the stimulus.
post_main:

Used for any final act after the main phase.

pre_shutdown: This phase acts as a buffer to apply any stimulus before the shutdown phase starts.
shutdown:
The shutdown phase is to ensure that the effect of stimulus generated during the main phase has propagated through the DUT and that the resultant data has drained away. It might also be used to execute the time-consuming sequences that read status registers.
post_shutdown:
post_shutdown is intended for any final activity before exiting the run phase. After this, UVM Testbench starts the cleanup phase.

3) Clean up Phase:
The cleanup phases are used to extract information from Scoreboards and Functional Coverage Monitors to determine whether the test case has passed and/or reached its coverage goals. The cleanup phases are implemented as functions and therefore take zero time to execute. They work from the bottom to the top of the component hierarchy.

extract:
The extract phase is used to retrieve and process information from Scoreboards and Functional Coverage Monitors. This may include the calculation of statistical information used by the report phase. This phase is usually used by Analysis side components.
check:

This phase is also used by the Analysis Components. This phase is used to check if the DUT behaved correctly and to find any error that may have occurred during the stimulus execution.
report:
The report phase is used to display the results of the simulation to the standard output or to write the results to file. This phase is usually used by Analysis Components.
final:

The final phase is used to complete any other outstanding actions that the Testbench has not already completed.

So these are all the different phases through which a Standard UVM Testbench runs through to generate a reset, doing configuration, stimulus generation & performing simulation and finally report generation.

so these were all different phases a UVM static component like Driver or Monitor etc. & dynamic component like Sequences goes through during life time of UVM Simulation.

//more about dynamic and static components (to be updated)






Short Notes :
1. build - Depending on configuration and factory settings, create and configure additional component hierarchies.
2. connect - Connect ports, exports, and implementations (imps), TLM ports connection
3. end_of_elaboration - Perform final configuration, topology, connection,
and other integrity checks.
4. start_of_simulation - Do pre-run activities such as printing banners, pre-loading memories, etc.
5. run - Most verification is done in this time-consuming phase. May fork other processes. Phase ends when global_stop_request is called explicitly or using phase drop objection mechanism
i) Time-consuming phase, so we can use task here
ii) run tasks are executed in parallel
iii) 12 sub-phases added in parallel with run_phase
iv) driver and monitor use run_phase for sure
6. extract - Collect information from the run in preparation for checking
7. check - Check simulation results against expected outcome.
8. report - Report simulation results.

uvm_phase is a base class which defines everything about the phase like behavior, state or context.

uvm_void > uvm_object > uvm_phase (class hierarchy)

• uvm_void 
• uvm_object extends uvm_void
• uvm_phase extends uvm_object

Constructor : new, get_phase_type


UVM flow :

1. We call run_test in tb_top, which calls the run_test task of the uvm_root class.
2. The uvm_root calls the m_run_phases task of the uvm_phase class.
3. For each phase, the execute_phase task is called.
4. If the phase is a top-down or bottom-up phase, exec_func is called for each component.
5. For example, the exec_func calls the build_phase function of each component.
6. If the phase is a task phase, exec_task is called for each component.
7. For example, the exec_task calls the main_phase task of each component.
8. The uvm_phase checks if any objections are raised by the components. The phase_done is the uvm_objection object that the uvm_phase keeps track of the number of objections with. When we called phase.raise_objection() from inside the run_phase of the test phase_done.raise_objection() is called in the uvm_phase under the hood.
9. If no objection is raised, all the processes started by the exec_task are killed. In other words, unless an objection is raised, the phase is immediately killed!
10. The steps 3 to 9 repeat until all phases are executed.

check for more details :
http://cluelogic.com/2014/08/uvm-tutorial-for-candy-lovers-phasing/



Thanks!  feedback/suggestions/edit_suggestions are most welcome

source of info: http://www.learnuvmverification.com/index.php/2016/04/29/uvm-phasing and uvm class reference manual and my understanding.