The need of clocking blocks in testbench

The need of clocking blocks?
Clocking blocks have been introduced in SystemVerilog to address the problem of specifying the timing and synchronization requirements of a design in a testbench.
1) It is used to specify synchronization characteristics of the design
2) It Offers a clean way to drive and sample signals
3) It provides race-free operation if input skew > 0
4) It helps in testbench driving the signals at the right time
5) Features
    - Clock specification
    - Input skew,output skew
    - Cycle delay (##)
6) Can be declared inside interface,module or program

Example :

view sourceprint?

01.Module M1(ck, enin, din, enout, dout);

02.input         ck,enin;

03.input  [31:0] din    ;

04.output        enout  ;

05.output [31:0] dout   ;

06. 

07.clocking sd @(posedge ck);

08.input  #2ns ein,din    ;

09.output #3ns enout, dout;

10.endclocking:sd

11. 

12.reg [7:0] sab ;

13.initial begin

14.sab = sd.din[7:0];

15.end

16.endmodule:M1


#Skew : it is related to set up and hold time.

Input and Output Skew :

A skew number for an input denotes when that input is sampled before the clocking event (such as posedge or negedge) occurs. 

For an output, it is just the opposite - it denotes when an output is synchronized and sent after the clocking event.

clocking clock1 @(posedge clk1);
   input a1, a2;
   output b1;
endclocking

In this case, the default input skew is 1step and the default output skew is 0.

Overwriting default skews

Even if there is a default statement for skews in a clocking block, it can be overwritten later in the block. For example, the example below overwrites the default input skew for signal a1 (to 1step) and output b1 (to 5 ns), but the input skew for a2remains unchanged at 2 ns.

 
clocking clock1 @(posedge clk1);
   default input #2ns output #3ns;
   input #1step a1;
   input a2;
   output #5ns b1;
endclocking