1. An Assertion specifies the behaviour of the system.
2. It validates the behaviour of design
3. In addition, assertion can be used to provide functional coverage and generate input stimulus for validation
The advantage of assertion:
1. Improving observability
2. reduce the debug time
3. bugs can be found earlier and more isolated
4. can interact with C function
types of assertion:
1.Immediate
2. concurrent
Immediate concurrent
based on simulation event based on a clock cycle
used without property keyword used with property keyword
placed in procedure block definition placed in procedural blocks, modules, interfaces or program definition
i) Immediate assertions are useful for combinational expression, similar to if else statement but with assertion control.
ii) Assertions are non-synthesizable
iii) Assertions can be written in design and TB both but in design, while synthesising need to remove so use `define
Difference between assert and cover :
assert: if you want scenario to be hold true then you write an assertion.
cover : Whether scenario ever happened in your simulation or not.
|-> implication operator
2. It validates the behaviour of design
3. In addition, assertion can be used to provide functional coverage and generate input stimulus for validation
The advantage of assertion:
1. Improving observability
2. reduce the debug time
3. bugs can be found earlier and more isolated
4. can interact with C function
types of assertion:
1.Immediate
2. concurrent
Immediate concurrent
based on simulation event based on a clock cycle
used without property keyword used with property keyword
placed in procedure block definition placed in procedural blocks, modules, interfaces or program definition
i) Immediate assertions are useful for combinational expression, similar to if else statement but with assertion control.
ii) Assertions are non-synthesizable
iii) Assertions can be written in design and TB both but in design, while synthesising need to remove so use `define
Difference between assert and cover :
assert: if you want scenario to be hold true then you write an assertion.
cover : Whether scenario ever happened in your simulation or not.
|-> implication operator
sequence s; @(posedge clk) a ##1 b; endsequence property p; a |-> s; endproperty assert property (p); cover property (p);
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