Formal verification is a technique used in different stages in ASIC project life cycle like front end verification, Logic Synthesis, Post Routing Checks and also for ECOs. But when you go deep into it, the formal verification used for verifying RTLs is entirely different from others. There are different formal techniques available as follows
Formal Equivalence Checking (LEC or logic equivalence checking)
Formal Property Checking.
Formal Equivalence can be used to verify if following models are equivalent:
1) RTL Design & Synthesized Netlist (Gate level model)
2) RTL Design & Reference Model
3) Two RTL designs
4) Two Gate level models
5) Two reference models
Tool Used for formal Verification - Jasper Gold
Formal Equivalence Checking (LEC or logic equivalence checking)
Formal Property Checking.
Formal Equivalence can be used to verify if following models are equivalent:
1) RTL Design & Synthesized Netlist (Gate level model)
2) RTL Design & Reference Model
3) Two RTL designs
4) Two Gate level models
5) Two reference models
Tool Used for formal Verification - Jasper Gold
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