uvm_component

1.The uvm_component class is the foundation of testbench structure,
examples :
i. uvm_monitor
ii. uvm_driver
iii. uvm_sequencer
iv. uvm_scoreboard

2. The UVM builds testbenches and runs them by calling the uvm phase methods in all components in a set order.
3.you define your component by overriding the phase methods and relying upon the UVM to call them in the right order
4.all uvm_component classes need a new () method with two arguments: name and parent

5. class hierarchy of uvm_component :
uvm_void > uvm_object > uvm_report_object > uvm_component
comaparison with uvm_seq_item :
uvm_void > uvm_object > uvm_transaction > uvm_sequence_item

Note : uvm_component exist throughout the simulation whereas uvm_transaction doesn't .

6. more information:
uvm_component provides the following interfaces:

1.Hierarchy provides methods for searching and traversing the component hierarchy.
2.Phasing defines a phased test flow that all components follow
3.Configuration provides methods for configuring component topology and other parameters ahead of and during component construction.
4.Reporting provides a convenience interface to the uvm_report_handler. All messages, warnings, and errors are processed through this interface.
5.Transaction recording provides methods for recording the transactions produced or consumed by the component to a transaction database (vendor specific).
6.Factory provides a convenience interface to the uvm_factory. The factory is used to create new components and other objects based on type-wide and instance-specific configuration.

7.Objection Interface These methods provide object level hooks into the uvm_objection mechanism.

The uvm_component is automatically seeded during construction using UVM seeding, if enabled. All other objects must be manually reseeded, if appropriate. See uvm_object::reseed for more information. (TBU)

for details of each interfaces :https://www.vmmcentral.org/uvm_vmm_ik/files3/base/uvm_component-svh.html

Note 2:
Transactions & Sequences are examples of Dynamic components while Driver & Sequencer are the examples of Static one

Note 3:
as we seen above uvm_component defines a phased test flow (all uvm phases) whereas uvm_transaction doesn't. that is why there is no phases in uvm sequences and sequence item.

I am trying to write a separate post for each UVM components, feedback/suggestions are most welcome.

Thanks!