Amba AXI is targeted at high performance, suitable for high-speed submicron connect.
Features:
1.separate address/control and data phases
2.support for unaligned data transfer using byte strobes
3. It is backwards compatible with existing AHB and APB interface
Architecture:
1. AXI Protocol is burst based
2. Every transaction has address and control information on the address channel
3. There are 5 channels.
1 . Difference between AXI3 and AXI4
AXI3 Vs AXI4 The difference between AXI3 and AXI4
1. AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to 256 beats.
2. AXI3 supports write interleaving. AXI4 does NOT support write interleaving
3. AXI3 supports locked transfers, AXI4 does NOT support locked transfers
4. AXI4 supports QoS, AXI3 does NOT suppor QoS.
I have seen many IP providers e.g. Synopsys supporting burst lengths up to 256 beats in AXI3
I have also seen many IP providers e.g. Synopsys NOT supporting write interleaving in AXI3.
Looks like the industry norm is to use AXI3 with burst lenghts up to 256 beats without support for write Interleaving.
2. why there is no separate response channel for read burst ?
I would guess it is because the VALID/READY handshake mechanism only allows for traffic flow in one direction, so for read transactions the traffic flow is slave to master for both data and response, sharing a VALID/READY handshake, whereas for write transactions the data is master to slave, but the response is slave to master, hence the response needing a separate channel to support the required VALID/READY controls.
Difference between AHB and AXI?
What is AXI Lite?
Name five special features of AXI?
Why streaming support,it's advantages?
Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high?
Explain AXI read transaction
What is the AXI capability of data interleaving?
Explain out-of-order transaction support on AXI?
Explain multiple outstanding address pending?
Any flow control mechanism in AXI?
How to ensure data integrity on AXI?
What is 'last' signal?
What are bursts and transfers?
Maximum size of a transfer?
Write response codes?
What is strobing in AXI?
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
Answer : All of the AXI channels pass information in only 1 direction (only the xREADY signal goes against the channel direction), so for a slave to give a response back to the master for a write transaction, would need a separate channel.
I guess this channel could have been defined to include a BRESP for each write data item, but this would increase the bandwidth requirement for this channel, and as in most applications you will just repeat the complete transaction for a non-OKAY response, few applications would make use of the additional detail of which transfer in a write burst caused a failure.
You do give a RRESP response for each read data item because the higher bandwidth channel is already there,
2) How to terminate A read/write burst ? Specification says we can not stop bursts intermittantly.
Answer : Simple answer, you cannot.
As soon as the AXI master indicates that it will perform X number of transfers in a transaction, it must complete X transfers. There is no "Early Burst Termination" concept like there was in AHB.
For write transactions the master could complete the burst, but driving the WSTRB bits all to logic '0' (dummy accesses) so that no data is actually being transferred to the slave, but for read transactions there is no equivalent, and so "real" read accesses will be completed.
In AHB Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.
3) Can A master can give WLAST in middle of a burst transfer ?
Answer : No. WLAST can only be asserted while WVALID is high when the final WDATA of a burst is being transferred. Indicating WLAST (and WVALID) too early in a burst would be a protocol violation.
Also, many slave designs will not use the WLAST input, and will simply count data items coming in, so this would not be a safe (or legal) method of terminating a burst.
4) in the same way if slave assersts RLAST before the completion of a busrt read?
Answer : If the slave drives RLAST (and RVALID) too early, this too is a protocol violation, and just as for the WLAST signal, some masters might not be monitoring RLAST, so this illegal use could be missed anyway.
5) If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and RLAST because we are getting individual beat responses anyway?
WLAST and RLAST can be used by masters and slaves that need to be told when the final data in a burst is being transferred.
Most masters and slaves will count the data coming in against how many transfers were indicated on AWLEN and ARLEN, so in these designs the xLAST inputs would not be required.
However to support all master and slave designs, masters must always drive WLAST when appropriate, and slaves must drive RLAST.
6 ) Whats the exact use of Exclusive Read and Write Pair transaction? Where exactly these will be used?
Semaphore passing: Semaphore passing is a software requirement, whereas my background is hardware, so please forgive any vagueness in the following answer.
If you have a shared area of memory used for passing control information between masters (or processes running on a master), you want to make sure that you complete the READ/WRITE sequence without another master changing the shared location.
If your master read the shared memory location, and it was changed by another master before your master could complete the subsequent write to that location, the interim write from the other master would be lost, which could have an impact on how your system works (control information lost)
So Exclusive Accesses are a hardware mechanism to support the software, indicating to the master when it did have uninterrupted access to the shared location, meaning that no write accesses from other masters will be accidentally overwritten.
7) Is there a possibility that A Read transaction can complete in One Cycle?
Section 3.1.4 on 3.4 says that "A default ARREADY value of LOW is possible but not recommended, because it implies that the transfer takes at least two cycles, one to assert ARVALID and another to assert ARREADY"
No.
It would take a minimum of 1 clock cycle to pass the address from the master to the slave (assumes ARREADY was high when ARVALID was asserted), and then a minimum of 1 clock cycle to pass the data from the slave to the master (assumes RREADY was high when RVALID was asserted).
If ARREADY is initially low when an address is signaled on ARVALID, it will take one clock cycle for the slave to sample this ARVALID and then assert ARREADY (if it can accept the address), and the address handshake then completes on the next clock rising edge (when both ARREADY and ARVALID are high). So 2 clock cycles just to pass the address from master to slave if ARREADY defaults to LOW.
It would then take at least a further clock cycle before the read data could be returned to the master.
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Exclusive access in AXI protocol
This mechanism enables the implementation of semaphore type of operation without requiring the bus to remain the locked to a particular master for the duration of the operation.
the advantage of exclusive access is that semaphore type operation does not impact either critical bus access latency or the maximum achievable bandwidth.
four Atomic access: Normal, exclusive, locked and reserved
the signal name for atomic access: AWLOCK n ARLOCK
consider a system in which two AXI master devices are using shared memory and as a system designer, you always will make sure that at a time your one master does not overwrite your memory written by another master.
Consider AXI Master 1 (M1) has initiated exclusive read transaction for address location 12'h100 to 12'h10F. Now slave will start monitoring these addresses for ARID given by M1. Now till exclusive write operation is performed slave monitors that address and if that address is changed by another master M2, it will give an indication of exclusive access failure during the exclusive write transaction and memory will not get updated by M1.
How it works:
What happened in above scenario is that Slave has reserved some memory resource for M1 virtually by given exclusive read request from the master. When the master comes for write transaction for that memory location slave will allow writing that memory resource only if another master device is not using that memory resource other wise data is not written to the memory resource.
So we can avoid memory overwrite problem for shared memory using EXCLUSIVE Access in AXI.
Consider AXI Master 1 (M1) has initiated exclusive read transaction for address location 12'h100 to 12'h10F. Now slave will start monitoring these addresses for ARID given by M1. Now till exclusive write operation is performed slave monitors that address and if that address is changed by another master M2, it will give an indication of exclusive access failure during the exclusive write transaction and memory will not get updated by M1.
How it works:
What happened in above scenario is that Slave has reserved some memory resource for M1 virtually by given exclusive read request from the master. When the master comes for write transaction for that memory location slave will allow writing that memory resource only if another master device is not using that memory resource other wise data is not written to the memory resource.
So we can avoid memory overwrite problem for shared memory using EXCLUSIVE Access in AXI.
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