Tuesday, January 26, 2016

Data type in SV Part 4

1.Data types :
shortint, int, longint, bit , byte  //signed and 2 state (0 and 1)
logic, reg, time //unsigned and 4 state (0,1,X and Z)
integer  //signed and 4 state

2. user-defined datatype :
class, enumerations, struct, unions, typedef

3.Enumerations :  it is strongly typed and if we want to insert error. also if we don't initialize, then each one will have unique value .

methods : first, last, next, prev, name

4. Structured and Unions :
In structures we can have different data types which we can't have in array.

Diff between structures  and unions :
Same memory space is allocated for every members in UNIONS while in case of structures different mem space is allocated for each data members .

struct {int a; byte b; bit [7:0] c;} my_data ;

memory allocation for the above defined struct "my_data_struct". 
 


union { int a; byte b; bit [7:0] c; } my_data; 
Memory allocation for the above defined union "my_data_union". 



5. Typedef :
It lets us define our own identifiers
typedef bit[3:0] nibble ;
advantage :  reusable, shorter name, less error prone



Data type in SV - Part 3 : Arrays and Queues

Array :
Arrays hold a fixed number of equally-sized data elements. 
Individual elements are accessed by index using a consecutive range of integers. 
Some type of arrays allows to access individual elements using non consecutive values of any data types.
can be classified as fixed-sized/static arrays whose size cannot change once their declaration is done, or dynamic arrays, which can be resized. 

A.Fixed-Size Arrays : 
size is fixed

int low_high[0:15]   //16 ints 0 .... 15
int ary[16]   //16 ints 0 .... 15, in C style

Packed Array :
reg [0:10] ary  //Packed array, ary is a variable here ,
wire [31:0][1:0] ary  //2D Packed array, ary is a variable here ,

reg [31:0] ary1 [0:255] //unpacked array of 256 registers 
reg [31:0] ary1 [256] // register is packed 32 bit wide

 storage of an unpacked array : 


Array methods :
1. array querying method // $left. $right, $low, $high, $increment, $size
2. array locator method
2. array reduction method  //sum, product, or, and ,xor
3. array ordering method  // reverse, sort(in ascending order), rsort(in descending order), shuffle
4. array index querying            



B. Dynamic Array : 
1.It is an unpacked array
2. size can be set during run time .
3. this is done basically to avoid wasting of memory
4. It is used to deal with continuous collection of variables

integer ary1[] ; // declaration
ary1 = new [10] ; // allocation of memory

ary1 = new[10] ('{4,5,6,7,8,9})  // initialization ... here array elements are 4,5,6,7,8,9,9,0,0,0,0
ary1 = new[15] ary2   // resizing of ary1

if we want to copy the elements from different array

ary2 = new [100] ary1   //prev. ary1 elements will be reserved


C.Assosiative Arrays : when the size of collection is unknown or the data space is sparse, associatove array is better option,
it ensures faster access .

int ary [*]  ; //wildcard index (any integral type)
int ary[string];  //string index
int ary[class];   //class index
int ary[integer]; // integer ,,

here string, class or integer is called "keytype"
ary // array name
int // data type

No need to use new method for mem declaration ins case of associative array
methods : num/size, delete, exists, first, last, next, prev


4.Queues : 
1.variable size
2. ordered collection of homogeneous element
3. can be passed to tasks/functions as ref or non-ref arguments

int q[$] = {1,2,3} ;
int q[$]   // queue declaration
int e, pos ;
e = q[0]  // first element
e = q[$]  // last element

p = q //copy

Methods : size, insert, popfront, pop=back, push-front, push-back

Dynamic array of queues :
typedef int q[$] ;
q ary[]   ; // array of queues


Queues of queue :
typedef int q[$] ;
q p[$] ;


COMPARISON OF ARRAYS   // from testbench.in

Static Array 
Size should be known at compilation time. 
Time require to access any element is less. 
if not all elements used by the application, then memory is wasted.
Not good for sparse memory or when the size changes. 
Good for contagious data. 


Associative Array 
No need of size information at compile time. 
Time require to access an element increases with size of the array.
Compact memory usage for sparse arrays. 
User don't need to keep track of size. It is automatically resized. 
Good inbuilt methods for Manipulating and analyzing the content. 

Dynamic Array
No need of size information at compile time. 
To set the size or resize, the size should be provided at runtime. 
Performance to access elements is same as Static arrays. 
Good for contagious data. 
Memory usage is very good, as the size can be changed dynamically. 



Queues 
No need of size information at compile time. 
Performance to access elements is same as Static arrays. 
User doesn't need to provide size information to change the size. It is automatically resized. 
Rich set of inbuilt methods for Manipulating and analyzing the content. 
Useful in self-checking modules. Very easy to work with out of order transactions. 
Inbuilt methods for sum of elements, sorting all the elements. 
Searching for elements is very easy even with complex expressions.
Useful to model FIFO or LIFO. 




If your code accidently tries to read from an out-of-bounds address, System-
Verilog will return the default value for the array element type. That just means
that an array of 4-state types, such as logic , will return X’s, whereas an array of
2-state types, such as int or bit , will return 0. This applies for all array types –
fi xed, dynamic, associative, or queue, and also if your address has an X or Z. An
undriven net is Z.If your code accidently tries to read from an out-of-bounds address, System-
Verilog will return the default value for the array element type. That just means
that an array of 4-state types, such as logic , will return X’s, whereas an array of
2-state types, such as int or bit , will return 0. This applies for all array types –
fi xed, dynamic, associative, or queue, and also if your address has an X or Z. An
undriven net is Z.


Data type in SV : part 2 (The logic type )

The Logic type :

1. In verilog we use two reg and wire for driving a port and connecting a block respectively .

2.Wire is used to connect gates or modules and are physical wire in a circuit and it must be driven by a continues assignment statements.

3.“Reg” in Verilog is a data object that holds its value from one procedural statement to next. When we say "reg (register datatype)" it does not mean the register in the hardware or a physical register in circuit. This is the common mistake or assumption mostly engineers thinks while learning Verilog.

4.In SV reg and wire are replaced with a single data type that is logic.
5.It is 4 state (1, 0, X, Z) System Verilog data type.

6.“logic” signal can be used anywhere a “net” used but there is one exception to this, you can not drive logic variable from multiple driver. Logic type can only have a single drive,

7. This means we can declare all signal as logic to find if is there any multiple driver issue. Because in this case you should be able to see compilation issue if there is any multiple driver by declaring all signal with type “logic”.
8. The signal you would like to have multiple drivers shall be declared as net type such as “wire” or “tri”

Data types in SV : Part 1

#System Verilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays: reduced memory usage, built-in support
for searching and sorting
• Classes and structures: support for abstract data structures
• Unions and packed structures: allow multiple views of the same data
• Strings: built-in string support
• Enumerated types: code is easier to write and understand

#Verilog-1995 has two basic data types:
1. variables and nets, both which hold 4-state , values: 0, 1, Z, and X.
2. RTL code uses variables to store combinational and sequential
values.
3. Variables can be unsigned single or multi-bit ( reg [7:0] m ), signed
32-bit variables ( integer ), unsigned 64-bit variables ( time ), and floating point
numbers ( real ).
4. Variables can be grouped together into arrays that have a fixed
size.
5. A net is used to connect parts of a design such as gate primitives and module
instances.
6. Lastly, all storage is static, meaning that all variables are alive for the entire simulation and routines cannot use a stack to hold arguments and local values. 7. #Verilog-2001 allows you to switch between static and dynamic storage, such as stacks.
# SystemVerilog adds many new data types to help both hardware designers and
verification engineers.

Note : int i ; //  2 state , 32 bit signed integer
Signed variables can cause unexpected
results with randomization, will discuss more about it later



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