Data types in SV : Part 1

#System Verilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays: reduced memory usage, built-in support
for searching and sorting
• Classes and structures: support for abstract data structures
• Unions and packed structures: allow multiple views of the same data
• Strings: built-in string support
• Enumerated types: code is easier to write and understand

#Verilog-1995 has two basic data types:
1. variables and nets, both which hold 4-state , values: 0, 1, Z, and X.
2. RTL code uses variables to store combinational and sequential
values.
3. Variables can be unsigned single or multi-bit ( reg [7:0] m ), signed
32-bit variables ( integer ), unsigned 64-bit variables ( time ), and floating point
numbers ( real ).
4. Variables can be grouped together into arrays that have a fixed
size.
5. A net is used to connect parts of a design such as gate primitives and module
instances.
6. Lastly, all storage is static, meaning that all variables are alive for the entire simulation and routines cannot use a stack to hold arguments and local values. 7. #Verilog-2001 allows you to switch between static and dynamic storage, such as stacks.
# SystemVerilog adds many new data types to help both hardware designers and
verification engineers.

Note : int i ; //  2 state , 32 bit signed integer
Signed variables can cause unexpected
results with randomization, will discuss more about it later