VLSI Knowledge Transfer: November 2012

Friday, November 30, 2012

UVM video lactures link

http://videos.accellera.org/uvmreadysetdeploy/uvm38mtR57B/index.html

1. We cannot pass a port (interface) directly in a class, so we use the concept of the virtual interface that points to the actual interface and can be passed in a class as a class is a dynamic entity.

2. The interface is used for connection of two modules.

3. The virtual interface is used to connect a class (dynamic entity) to a module (static entity)

4. Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design.

5. A virtual interface allows the same subprogram to operate on different portions of a design and to dynamically control the set of signals associated with the subprogram.

6. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be rewritten.

7. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote code reuse.

8. Virtual interfaces can be declared as class properties, which can be initialized procedurally or by an argument to new(). This allows the same virtual interface to be used in different classes.

8. In UVM based environment we can set the virtual interface using config_db in the tb_top and then it will be available down the hierarchy.

9. The following example shows how the same transactor class can be used to interact with various different devices:

interface SBus; // A Simple bus interface

logic req, grant;

logic [7:0] addr, data;

endinterface

class SBusTransctor; // SBus transactor class

virtual SBus bus; // virtual interface of type Sbus

 07 function new( virtual SBus s );

bus = s; // initialize the virtual interface

endfunction

task request(); // request the bus

bus.req <= 1'b1;

endtask

task wait_for_bus(); // wait for the bus to be granted

@(posedge bus.grant);

endtask

endclass

module devA( Sbus s ) ... endmodule // devices that use SBus

module devB( Sbus s ) ... endmodule

module top;

SBus s[1:4] (); // instantiate 4 interfaces

devA a1( s[1] ); // instantiate 4 devices

devB b1( s[2] );

devA a2( s[3] );

devB b2( s[4] );

initial begin

SbusTransactor t[1:4]; // create 4 bus-transactors and bind

t[1] = new( s[1] );

t[2] = new( s[2] );

t[3] = new( s[3] );

t[4] = new( s[4] );

 end

endmodule

In the preceding example, the transaction class SbusTransctor is a simple reusable component. It is written without any global or hierarchical references and is unaware of the particular device with which it will interact. Nevertheless, the class can interact with any number of devices (four in the example) that adhere to the interface’s protocol.

Notes :
1. virtual i/f is just a handle (like pointers) when a virtual i/f is declared, it only creates handles, doesn't create a local interface.

2. Virtual interface variables can be passed as arguments to tasks, functions, or methods. A single virtual interface variable can thus represent different interface instances at different times throughout the simulation.

3. A virtual interface must be initialized before it can be used; it has the value null before it is initialized.

Benefits of using interface :
1. can contain protocol checking using assertions and functional coverage blocks.
2. maintainability and reusability.
3. can contain tasks and functions.

Friday, November 23, 2012

Post 16: Why virtual class

http://www.systemverilog.in/forum/showthread.php?tid=143

Post 14 : Introduction to OOPs

OOP Can be described with following concepts :

Follows bottom up approach.
Emphasis is on data. //need to search explanation
Programs are divided into objects.
Functions and data are bound together.
Communication is done through objects.
Data is hidden.

The following are the basic concepts of OOPs:
Classes, Objects, Data abstraction and encapsulation, Polymorphism, Inheritance, Message Passing, and Dynamic Binding.

1. What is a class?
Class is an entity which consists of member data and member functions which operate on the member data bound together.

2. What is an object?
i)Objects are instances of classes.
ii) Class is a collection of similar kind of objects.
iii) When a class is created it doesn’t occupy any memory
iv) but when instances of class is created i.e., when objects are created they occupy memory space.

3. What is encapsulation?
Encapsulation is welding of code and data together into objects.

4. What is inheritance?
Inheritance is a mechanism through which a subclass inherits the properties and behavior of its superclass.
The derived class inherits the properties and method implementations of the base class and extends it by overriding methods and adding additional properties and methods.

5. What is polymorphism?
i) In Greek this means "many shapes."
ii) As a consequence of inheritance and virtual functions, a single task (for example, drawing a geometrical shape) can be implemented using the same name (like draw()) and implemented differently (via virtual functions) as each type in object hierarchy requires(circle.draw() or rectangle.draw()).
iii) Later, when a polymorphic object (whose type is not known at compile time) executes the draw() virtual function, the correct implementation is chosen and executed at run time.

6. What is the difference between function overloading and function overriding?
i) Overloading is a method that allows defining multiple member functions with the same name but different signatures.
The compiler will pick the correct function based on the signature.

ii) Overriding is a method that allows the derived class to redefine the behavior of member functions which the derived class inherits from a base class.
The signatures of both base class member function and derived class member function are the same; however, the implementation and, therefore, the behavior will differ.

7. What are the advantages of OOP?

Data hiding helps create secure programs.
Redundant code can be avoided by using inheritance.
Multiple instances of objects can be created.
Work can be divided easily based on objects.
Inheritance helps to save time and cost.
Easy upgrading of systems is possible using object oriented systems.

8. Explain about the virtual task and methods .

#important : Virtual tasks and functions are the ways to achieve the polymorphism in system verilog.

Example :

class base ;

virtual function int print;

$display("INSIDE BASE \n");

endfunction : print

 

endclass : base

 

class derived extends base;

 

function int print;

$display("INSIDE DERIVED \n");

endfunction : print

 

endclass : derived

 

 

 

program test ;

 

derived d1;

initial

begin

d1 = new();

d1.print();

callPrint (d1);

end

 

task callPrint (base b1);

$display("Inside callPrint \n");

b1.print;

endtask : callPrint

 

endprogram

 

Output :

========

 

VSIM 1> run

# INSIDE DERIVED

#

# Inside callPrint

#

# INSIDE BASE

#

Thursday, November 22, 2012

UVM : Introduction

What is UVM

1)UVM is standardization in verification methodology by Accellera.
2) UVM is based on the best features in the existing methodologies OVM/VMM. But it is mostly derived from the OVM methodology and in fact it's backward compatible with the OVM. It has all the features of the proven OVM methodology
3) It is based on the System Verilog standard so it will compile on all the simulators which support the system Verilog standard.

The main advantages of UVM is :

1) Standardized verification methodology so no more confusion to choose a methodology to start a project.
2) No tool dependency. No more porting issues from one tool to other
3) Less confusion for the engineers. Easy to learn and maintain the skill set
4) Provides the flexibility and ways to connect the legacy VMM/OVM components
5) Backward compatible with OVM and provides the scripts to change OVM environment to UVM.
6) Remove the mess of having so many methodologies and provides a standard solution which compiles on all tools.

Universal Verification Methodology (From Wikipedia)

1. The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs.

2. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001.

3.The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc.,

History
1). lectronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1)[1], a verification methodology developed jointly in 2007 by Cadence Design Systems and Mentor Graphics.

2). On February 21, 2011, Accellera approved the 1.0 version of UVM[2]. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.[3].

The need of clocking blocks in testbench

The need of clocking blocks?
Clocking blocks have been introduced in SystemVerilog to address the problem of specifying the timing and synchronization requirements of a design in a testbench.
1) It is used to specify synchronization characteristics of the design
2) It Offers a clean way to drive and sample signals
3) It provides race-free operation if input skew > 0
4) It helps in testbench driving the signals at the right time
5) Features
    - Clock specification
    - Input skew,output skew
    - Cycle delay (##)
6) Can be declared inside interface,module or program

Example :

01.Module M1(ck, enin, din, enout, dout);

02.input         ck,enin;

03.input  [31:0] din    ;

04.output        enout  ;

05.output [31:0] dout   ;

06. 

07.clocking sd @(posedge ck);

08.input  #2ns ein,din    ;

09.output #3ns enout, dout;

10.endclocking:sd

11. 

12.reg [7:0] sab ;

13.initial begin

14.sab = sd.din[7:0];

15.end

16.endmodule:M1

 #Skew : it is related to set up and hold time.

Input and Output Skew :

A skew number for an input denotes when that input is sampled before the clocking event (such as posedge or negedge) occurs. 

For an output, it is just the opposite - it denotes when an output is synchronized and sent after the clocking event.

clocking clock1 @(posedge clk1);
   input a1, a2;
   output b1;
endclocking

In this case, the default input skew is 1step and the default output skew is 0.

Overwriting default skews
Even if there is a default statement for skews in a clocking block, it can be overwritten later in the block. For example, the example below overwrites the default input skew for signal a1 (to 1step) and output b1 (to 5 ns), but the input skew for a2remains unchanged at 2 ns.

clocking clock1 @(posedge clk1);
   default input #2ns output #3ns;
   input #1step a1;
   input a2;
   output #5ns b1;
endclocking

VLSI Interview Questions : Part 1

What are the differences between SIMULATION and SYNTHESIS
i)Simulation <= verify your design.

Simulation is used to verify the functionality of the circuit.
a)Functional Simulation: a study of ckt's operation independent of timing parameters and gate delays.

b) Timing Simulation: study including estimated delays, verify setup, hold and other timing requirements of devices like flip-flops are met.
ii)Synthesis <= Check for your timing

Synthesis: One of the foremost in back-end steps whereby synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives (equations as in CPLD) or components(as in FPGAs) to fit into the target technology.

Basically the synthesis tools convert the design description into equations or components

2. Differences between latches & flipflops?
There are 2 types of circuits:
1. Combinational
2. Sequential

Latches and flipflops both come under the category of "sequential circuits", whose output depends not only on the current inputs but also on previous inputs and outputs.
Difference: Latches are level-sensitive, whereas, FF are edge sensitive.
By edge sensitive, I mean O/p changes only when there is a clock transition.
( from 1 to 0 or from 0 to 1)

Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, the output won't change immediately. At time = 3 seconds, clock transition takes place. After that, O/P will change.

Flip-flops are of 2 types:
1. Positive edge triggered

2. negative edge triggered

1) Flip-flops take twice the number of gates as latches
2) so automatically delay is more for flipflops
3) power consumption is also more

# Imp: latch does not have a clock signal, whereas a flip-flop always does.

3. What is slack?
The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path.
Slack may be +ve or -ve.

4. RTL and Behavioral

i) Register transfer language means there should be data flow between two registers and logic is in between them for end registers data should flow.

ii) Behavioral means how hardware behave determine the exact way it works we write using HDL syntax.For complex projects it is better mixed approach or more behavioral is used.

5. Equivalence between VHDL and C?
i)There is a concept of understanding in C there is structure. Based upon requirement structure provide facility to store the collection of different data types.

ii) In VHDL we have direct access to memory so instead of using a pointer in C (and member of structure) we can write interface to store data in memory and access it.

Difference between wire, reg and logic

1). Wire and Reg are present in the Verilog
2). System Verilog adds one more data type called logic.

Wire :
1) Wire data type is used in the continuous assignments or ports list.
2) It is treated as a wire So it can not hold a value.
3) It can be driven and read.
4) Wires are used for connecting different modules.

Reg :
1) Reg is a data storage element in System Verilog.
2) It's not an actual hardware register but it can store values.
3) Register retain their value until next assignment statement.

Logic :
1) System Verilog added this additional datatype to make it easy to use the reg/wire datatype.
2) The main difference between logic datatype and reg/wire is that a logic can be driven by both continuous assignment or blocking/non-blocking assignment.

Source: asicguru.com (with little modification)

VLSI Knowledge Transfer