Difference between wire, reg and logic

1). Wire and Reg are present in the Verilog
2). System Verilog adds one more data type called logic.

Wire : 
1) Wire data type is used in the continuous assignments or ports list.
2) It is treated as a wire So it can not hold a value.
3) It can be driven and read.
4) Wires are used for connecting different modules.

Reg : 
1) Reg is a data storage element in System Verilog.
2) It's not an actual hardware register but it can store values.
3) Register retain their value until next assignment statement.

Logic : 
1) System Verilog added this additional datatype to make it easy to use the reg/wire datatype.
2) The main difference between logic datatype and reg/wire is that a logic can be driven by both continuous assignment or blocking/non-blocking assignment.

Source: asicguru.com (with little modification)